SDK Implementation
verified
compiles
partial
in progress
to implement
LLL
HHAL
CCore
TStudio
| Feature | Core.L STM32L011 | Core.U STM32L422 | Core.W STM32WBA55 | Core.H STM32H523 |
|---|---|---|---|---|
| System | ||||
| Ccore initialization | ||||
| TLED | ||||
| Tdelay (ms / µs) | ||||
| LSysTick | ||||
| fault handlers | ||||
| Clocks | ||||
| LHSI (internal RC) | ||||
| LHSE (external crystal) | ||||
| LMSI / MSIS (low-power) | ||||
| LPLL (high-speed) | ||||
| GPIO | ||||
| Tdigital I/O (read / write) | ||||
| TEXTI (external interrupts) | ||||
| Lalternate function config | ||||
| Copen-drain / pull config | ||||
| UART | ||||
| CTX / RX (polling) | ||||
| Cinterrupt-driven | ||||
| CDMA | ||||
| hardware flow control | ||||
| CLPUART (low-power) | ||||
| I2C | ||||
| Cstandard mode (100 kHz) | ||||
| Cfast mode (400 kHz) | ||||
| fast-mode plus (1 MHz) | ||||
| Cinterrupt-driven | ||||
| DMA | ||||
| C10-bit addressing | ||||
| SMBus mode | ||||
| SPI | ||||
| Cmaster TX / RX (polling) | ||||
| Cinterrupt-driven | ||||
| CDMA | ||||
| slave mode | ||||
| OctoSPI / QSPI | ||||
| Timers | ||||
| TPWM output | ||||
| Cinput capture | ||||
| one-shot pulse | ||||
| encoder mode | ||||
| LPTIM (low-power timer) | ||||
| TIWDG (watchdog) | ||||
| ADC | ||||
| Tsingle-shot raw read | ||||
| Tmillivolt read (VREFINT) | ||||
| Ttemperature sensor | ||||
| Cresolution (8 / 10 / 12-bit) | ||||
| Coversampling / burst | ||||
| CDMA | ||||
| Ccontinuous / scan mode | ||||
| analog watchdog | ||||
| Project Generation (Coregen) | ||||
| CGPIO pad auto-init | ||||
| CI2C auto-init | ||||
| Canalog pad init | ||||
| CSPI auto-init | ||||
| CUART auto-init | ||||
| Ctimer / PWM auto-init | ||||
| Power Management | ||||
| Csleep mode | ||||
| CSTOP mode | ||||
| Cstandby / shutdown | ||||
| TRTC wakeup | ||||
| CEXTI wakeup | ||||
| Cwakeup pin (Standby) | ||||
| TRTC Alarm A | ||||
| Tbackup registers | ||||
| Security | ||||
| hardware RNG | ||||
| AES (hardware) | ||||
| PKA / ECC | ||||
| HASH (SHA-256) | ||||
| Connectivity | ||||
| TUSB CDC serial | ||||
| USB HID | ||||
| USB MSC | ||||
| ROM DFU bootloader | ||||
| BLE radio | ||||
| BLE advertising | ||||
| BLE GATT server | ||||
| FDCAN | ||||
| Advanced | ||||
| I3C controller | ||||
| I3C target | ||||
| COMP (analog comparator) | ||||
| TDAC | ||||
“Compiles” = builds for that target but not run on physical hardware. Verification ongoing.
Roadmap
Hardware capabilities identified in the reference manuals (RM0377, RM0394, RM0481, RM0493) that are not yet implemented, ranked by general-platform usefulness and estimated effort.
Legend
on IC
partial / limited
not on IC
Useful:1=★2=★★3=★★★4=★★★★5=★★★★★
| Feature | Core.L | Core.U | Core.W | Core.H | Useful | Effort |
|---|---|---|---|---|---|---|
| Tier 1 — High Impact | ||||||
| SPI master (fix W, test H) | ★★★★★ | |||||
| SPI coregen auto-init | ★★★★★ | |||||
| LPTIM (low-power timer) | ★★★★★ | |||||
| UART IRQ + coregen | ★★★★★ | |||||
| Stop mode (L, W) | ★★★★★ | |||||
| Tier 2 — Valuable | ||||||
| I2C interrupt-driven | ★★★★★ | |||||
| SPI DMA | ★★★★★ | |||||
| LPUART (low-power UART) | ★★★★★ | |||||
| CRC hardware | ★★★★★ | |||||
| AES accelerator | ★★★★★ | |||||
| QUADSPI / OctoSPI | ★★★★★ | |||||
| TIM1 advanced (complementary PWM) | ★★★★★ | |||||
| Comparators (COMP) | ★★★★★ | |||||
| Flash ECC reporting | ★★★★★ | |||||
| GPDMA linked-list mode | ★★★★★ | |||||
| Tier 3 — Specialized | ||||||
| Peripheral autonomous mode (Stop) | ★★★★★ | |||||
| FDCAN | ★★★★★ | |||||
| I3C controller | ★★★★★ | |||||
| USB MSC (mass storage) | ★★★★★ | |||||
| USB Host mode | ★★★★★ | |||||
| SDMMC (SD card) | ★★★★★ | |||||
| SAI / I2S (audio) | ★★★★★ | |||||
| PKA / ECC | ★★★★★ | |||||
| HASH (SHA-256) | ★★★★★ | |||||
| TSC (touch sensing) | ★★★★★ | |||||
| TrustZone / MPU setup | ★★★★★ | |||||
| 802.15.4 (Thread / Zigbee) | ★★★★★ | |||||
IC availability reflects the specific WLCSP variant on each Core tile, not the full subfamily. Effort: fewer bars = less work. Derived from RM0377/RM0394/RM0481/RM0493 cross-referenced against SDK status.