Core.L.1
ultra-low-power Cortex-M0+
Ultra-low-power ARM Cortex-M0+ core tile built around the STM32L011E4 with 16KB flash, 2KB RAM, and 512 bytes of data EEPROM. Optimized for battery-powered and energy-harvesting applications, with flexible I/O across 14 pads including I2C, USART, and LPUART interfaces, 6 ADC inputs, multiple timer channels, and dual analog comparators. Runs from 1.8–3.6V with bootloading and hardware debug via SWD.
Product Info
- Status
- Beta
- In Stock
- 12
- Pricing
Qty Each 1+ $10.00 10+ $9.00 50+ $8.50
Technical Summary
Resources & Links
- Datasheet
- Download PDF
- JSON Tile Definition
- v0.20 (Feb 14, 2026)
- Drivers
- GitHub
- Discussion
- Discord
Application Notes
Single-Wire Debug & Bootloading
The single-wire debug port is available on pads 13 (SWCLK) and 14 (SWDIO). While not absolutely required, it is often helpful to have the ability to hold pads 22 (NRST) low when connecting to the debugger. You can likely also use BOOT0 to help the debugger connect.
LED
The onboard LED is connected to PA8 in an active-high configuration.
Pad Assignments
| Pad | ⏻ | D | A | I2C | USART | LPUART | ○ | ||
|---|---|---|---|---|---|---|---|---|---|
| 1 | GND | · | · | · | · | · | · | · | · |
| 2 | · | A3 | 3 | · | 2.RX | 1.RX | 21.2, 2.4 | · | COMP2.IN+ |
| 3 | · | A0 | 0 | · | 2.RX, 2.CRS | 1.RX | 2.1, 2.ETR, LP1.1 | · | COMP1.OUT, COMP1.IN- |
| 4 | · | B6 | · | 1.CLK | 2.TX | 1.TX | 2.3, LP1.ETR | · | COMP2.IN+ |
| 5 | · | B7 | · | 1.DAT | 2.RX | 1.RX | 2.4, LP1.2 | · | COMP2.IN+ |
| 6 | · | A1 | 1 | 1.SMBA | 2.RTS_DE | 1.TX | 2.2, 21.ETR, LP1.2 | · | COMP1.IN+ |
| 7 | · | A2 | 2 | · | 2.TX | 1.TX | 21.1, 2.3 | · | COMP2.OUT, COMP2.IN- |
| 8 | · | A5 | 5 | · | · | · | 2.1, 2.ETR, LP1.2 | · | COMP1.IN-, COMP2.IN- |
| 9 | · | B0 | 8 | · | 2.RTS_DE | · | 2.2, 2.3 | · | · |
| 10 | V+ | · | · | · | · | · | · | · | · |
| 11 | · | B9 | · | · | · | · | · | BOOT0 | · |
| 12 | · | · | · | · | · | · | · | NRST | · |
| 13 | · | A14 | · | 1.SMBA | 2.TX | 1.TX | LP1.OUT | SWCLK | COMP2.OUT |
| 14 | · | A13 | · | 1.DAT | · | 1.RX | LP1.ETR | SWDIO | COMP1.OUT |
I2C1
I2C- Mode
- master, slave
- Max Clock
- —
- Address
- programmable
- Format
- —
| Function | Required | Pad(s) |
|---|---|---|
| I2C1.CLK | No | 4 |
| I2C1.DAT | No | 5, 14 |
| I2C1.SMBA | No | 6, 13 |
USART2
USART- Mode
- Max Clock
- —
- Address
- —
- Format
- —
| Function | Required | Pad(s) |
|---|---|---|
| USART2.RX | No | 2, 3, 5 |
| USART2.CRS | No | 3 |
| USART2.TX | No | 4, 7, 13 |
| USART2.RTS_DE | No | 6, 9 |
LPUART1
LPUART- Mode
- Max Clock
- —
- Address
- —
- Format
- —
| Function | Required | Pad(s) |
|---|---|---|
| LPUART1.RX | No | 2, 3, 5, 14 |
| LPUART1.TX | No | 4, 6, 7, 13 |
Development Product — This is an electronic development module intended for evaluation, prototyping, and integration into other designs by qualified engineers and developers. It is not a finished consumer product and has not been independently certified for FCC, CE, UL, or other regulatory compliance. The integrator of this module into a finished product is responsible for obtaining all necessary certifications. Not intended for use in life-support systems, safety-critical applications, or any application where failure could result in personal injury or property damage. See our Terms of Sale for full details.