Core.U.2
expanded-I/0 USB-prog. Cortex-M4
The expanded-I/O USB-programmable Core.U.2 is based on the same 80-MHz Cortex-M4 STM32L422 as the smaller Core.U.1, with the top 12 pads (1-5 and 16-22) matching the pad layout of the Core.U.1. The additional I/O pads provide a user-configurable combination of single-wire and trace debugging, two I2C ports, one SPI port, one quad SPI port, ten 12-bit ADC inputs, multiple timers, capacitive-touch inputs, and an on-board comparator. The board also includes an onboard LED and a physical button for reset and bootloading (see Application Notes).
Product Info
- Status
- Production
- In Stock
- 17
- Pricing
Qty Each 1+ $15.00 10+ $13.50 50+ $12.75
Technical Summary
Resources & Links
- Datasheet
- Download PDF
- JSON Tile Definition
- v0.36 (Feb 14, 2026)
- Drivers
- GitHub
- Discussion
- Discord
Application Notes
USB Bootloading
Similar to the Core.U.1, when the chip is blank, it will default into the bootloader when connected over USB. Once there is code in the program space, you need to hold the BOOT0 pin low during reset (either power-on or via the NRST pin) to enter the bootloader. The physical button will also execute this behavior.
Single-Wire Debug & Bootloading
The single-wire debug port is available on pads 13 (SWCLK) and 14 (SWDIO). While not absolutely required, it is often helpful to have the ability to hold pads 22 (NRST) low when connecting to the debugger. You can likely also use BOOT0 (via either the pad or the button) to help the debugger connect.
Button
The board button will issue a software reset via the NRST pin when pressed for a short (less than ~1sec) time. When held for more than ~2 seconds and released, the system will enter the bootloader.
LED
The onboard LED is connected to PA8 in an active-high configuration.
Pad Assignments
| Pad | ⏻ | D | A | USB | I2C | SPI | QSPI | USART | LPUART | ○ | ||
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 1 | GND | · | · | · | · | · | · | · | · | · | · | · |
| 2 | · | A7 | 12 | · | 3.CLK | 1.M0SI | IO2 | · | · | 1.1N | · | · |
| 3 | · | A1 | 6 | · | 1.SMBA | 1.CLK | · | 2.RTS_DE | · | 2.2, 15.1N | · | COMP1.+ |
| 4 | · | B6 | · | · | 1.CLK | · | · | 1.TX | · | 16.1N, LP1.ETR | TRACE.D3 | G3.IO3 |
| 5 | · | B7 | · | · | 1.DAT | · | · | 1.RX | · | LP1.2 | TRACE.CK | G2.IO4 |
| 6 | · | A3 | 8 | · | · | · | CLK | 2.RX | 1.RX | 2.4, 15.2 | · | · |
| 7 | · | A2 | 7 | · | · | · | CS | 2.TX | 1.RX | 2.3, 15.1 | · | · |
| 8 | · | A0 | 5 | · | · | · | · | 2.CTS | · | 2.1, 2.ETR | · | COMP1.IN-, COMP1.OUT |
| 9 | · | A6 | 11 | · | · | 1.MISO | IO3 | · | 1.CTS | 1.BKIN, 16.1 | · | COMP1.OUT |
| 10 | · | A5 | 10 | · | · | 1.CLK | · | · | · | 2.1, 2.ETR, LP2.ETR | · | COMP1.IN- |
| 11 | · | B0 | 15 | · | · | 1.CS | IO1 | · | · | 1.2N | TRACE.D1 | COMP1.OUT |
| 12 | · | B3 | · | · | · | 1.CLK | · | 1.RTS_DE | · | 2.2 | TRACE.SWO | · |
| 13 | · | A14 | · | · | 1.SMBA | · | · | · | · | LP1.OUT | SWCLK | · |
| 14 | · | A13 | · | · | · | · | · | · | · | · | SWDIO | · |
| 15 | · | B1 | 16 | · | · | · | IO0 | · | · | 1.3N, LP2.1 | TRACE.D1 | · |
| 16 | · | A12 | · | DP | · | 1.MOSI | · | 1.RTS_DE | · | 1.ETR | · | · |
| 17 | · | A11 | · | DM | · | 1.MISO | · | 1.CTS | · | 1.4, 1.BKIN2, 1.BKIN2_COMP1 | · | COMP1.OUT, G2.IO1 |
| 18 | · | B4 | · | · | 3.DAT | 1.MISO | · | 1.CTS | · | · | · | · |
| 19 | · | A4 | · | · | · | 1.CS | · | · | · | LP2.OUT | · | COMP1.- |
| 20 | V+ | · | · | · | · | · | · | · | · | · | · | · |
| 21 | · | PH3 | · | · | · | · | · | · | · | · | BOOT0 | · |
| 22 | · | · | · | · | · | · | · | · | · | · | NRST | · |
USB
USB- Mode
- Max Clock
- —
- Address
- —
- Format
- —
| Function | Required | Pad(s) |
|---|---|---|
| D+ | Yes | 16 |
| D- | Yes | 17 |
I2C1
I2C- Mode
- master, slave
- Max Clock
- 1MHz
- Address
- programmable
- Format
- 7-bit address
| Function | Required | Pad(s) |
|---|---|---|
| I2C1.CLK | Yes | 4 |
| I2C1.DAT | Yes | 5 |
| I2C1.SMBA | No | 3, 13 |
I2C3
I2C- Mode
- master, slave
- Max Clock
- 1MHz
- Address
- programmable
- Format
- 7-bit address
| Function | Required | Pad(s) |
|---|---|---|
| I2C3.CLK | Yes | 2 |
| I2C3.DAT | Yes | 18 |
SPI1
SPI- Mode
- master, slave
- Max Clock
- 40Mhz (master), 20MHz (slave)
- Address
- —
- Format
- —
| Function | Required | Pad(s) |
|---|---|---|
| SPI1.CLK | No | 3, 10, 12 |
| SPI1.MOSI | No | 2, 16 |
| SPI1.MISO | No | 9, 17, 18 |
| SPI1.CS | No | 11, 19 |
QSPI
QSPI- Mode
- Max Clock
- —
- Address
- —
- Format
- —
| Function | Required | Pad(s) |
|---|---|---|
| QSPI.IO2 | Yes | 2 |
| QSPI.CLK | Yes | 6 |
| QSPI.CS | Yes | 7 |
| QSPI.IO3 | Yes | 9 |
| QSPI.IO1 | Yes | 11 |
| QSPI.IO0 | Yes | 15 |
USART1
USART- Mode
- Max Clock
- —
- Address
- —
- Format
- —
| Function | Required | Pad(s) |
|---|---|---|
| USART1.TX | Yes | 4 |
| USART1.RX | Yes | 5 |
| USART1.RTS_DE | No | 12, 16 |
| USART1.CTS | No | 17, 18 |
USART2
USART- Mode
- Max Clock
- —
- Address
- —
- Format
- —
| Function | Required | Pad(s) |
|---|---|---|
| USART2.RTS_DE | No | 3 |
| USART2.RX | No | 6 |
| USART2.TX | No | 7 |
| USART2.CTS | No | 8 |
| USART2.CK | No | 19 |
LPUART1
LPUART- Mode
- Max Clock
- —
- Address
- —
- Format
- —
| Function | Required | Pad(s) |
|---|---|---|
| LPUART1.RX | No | 6 |
| LPUART1.TX | No | 7 |
| LPUART1.CTS | No | 9 |
| LPUART1.RTS_DE | No | 16 |
Development Product — This is an electronic development module intended for evaluation, prototyping, and integration into other designs by qualified engineers and developers. It is not a finished consumer product and has not been independently certified for FCC, CE, UL, or other regulatory compliance. The integrator of this module into a finished product is responsible for obtaining all necessary certifications. Not intended for use in life-support systems, safety-critical applications, or any application where failure could result in personal injury or property damage. See our Terms of Sale for full details.