Core.W
BLE-enabled 100MHz Cortex M33
The Core.W tile combines the powerful STM32WBA55 100-MHz 32-bit Cortex-M33 processor together with an integrated 2.4GHz antenna on double-size T48 (4.0 x 8.0 mm) SMD package. The tile provides a user-configurable combination of: SW debug & bootloading; 1MB flash & 128KB SRAM; wireless communications (BLE 5.4, Thread, Matter, Zigbee, proprietary); two FM+ (1MHz) I2C ports; two SPI ports; one USART; five 12-bit 2.5Msps ADC inputs (16-bit with oversampling); many timers; ten capacitive touch inputs; one serial-audio interface; IR output; and an on-board LED
Product Info
- Status
- Production
- In Stock
- 35
- Pricing
Qty Each 1+ $20.00 10+ $18.00 50+ $17.00
Technical Summary
Resources & Links
- Datasheet
- Download PDF
- JSON Tile Definition
- v0.22 (Feb 14, 2026)
- Drivers
- GitHub
- Discussion
- Discord
Application Notes
Single-Wire Debug & Bootloading
The single-wire debug port is available on pads 13 (SWCLK) and 14 (SWDIO). While not absolutely required, it is often helpful to have the ability to hold pads 22 (NRST) low when connecting to the debugger. You can likely also use BOOT0 to help the debugger connect.
Antenna Clearance
For the best wireless performance, the antenna-end of the Tile (the end without any pads) should not have any copper traces or planes above or below it.
LED
The onboard LED is connected to PB12 in an active-high configuration.
Pad Assignments
| Pad | ⏻ | D | A | I2C | SPI | SAI | USART | IF | ○ | ||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 1 | GND | · | · | · | · | · | · | · | · | · | · |
| 2 | · | A0 | 9 | · | 3.CLK | · | · | · | 1.2N, 3.3, 3.ETR, LP1.IN1 | · | G2.IO2 |
| 3 | · | A5 | 4 | · | 3.CS | 1.D2 | · | · | 2.1, LP2.ETR | · | G1.IO4 |
| 4 | · | A6 | 3 | 3.CLK | · | 1.CK2, 1.MCLK_A | · | · | 2.4 | · | G1.IO3 |
| 5 | · | A7 | 2 | 3.DAT | · | 1.SCK_A | · | · | 2.3 | · | G1.IO2 |
| 6 | · | B8 | · | · | 3.MOSI | · | 2.RX | · | 1.1, 3.ETR, 16.1N, LP1.ETR | · | G2.IO4 |
| 7 | · | B9 | 10 | · | 3.MISO | · | · | IR_OUT | 1.3N, 3.4, 16.1, LP2.IN1 | · | G2.IO3 |
| 8 | · | A12 | · | · | 1.CS | · | 2.TX | · | 1.2 | · | G3.IO4 |
| 9 | · | B4 | · | · | 1.CLK | 1.MCLK_B | 2.RX | · | 1.3, 17.1, LP2.IN2 | · | G3.IO1 |
| 10 | · | A15 | · | 1.CLK | 1.MOSI | · | 2.RTS_DE | · | 1.ETR, LP1.2 | · | · |
| 11 | · | B3 | · | 1.DAT | 1.MISO | · | 2.CK | · | 1.4, 171.N, LP1.IN2 | · | G3.IO2 |
| 12 | · | A13 | · | · | · | · | · | · | 17.BKIN | SWDIO | G3.IO3 |
| 13 | · | A14 | · | · | · | · | 2.TX | · | · | SWCLK | · |
| 14 | V+ | · | · | · | · | · | · | · | · | · | · |
| 15 | · | H3 | · | · | · | · | · | · | · | BOOT0 | · |
| 16 | · | · | · | · | · | · | · | · | · | NRST | · |
I2C1
I2C- Mode
- master, slave
- Max Clock
- 1MHz
- Address
- programmable
- Format
- —
| Function | Required | Pad(s) |
|---|---|---|
| I2C1.CLK | Yes | 10 |
| I2C1.DAT | Yes | 11 |
I2C3
I2C- Mode
- master, slave
- Max Clock
- 1MHz
- Address
- programmable
- Format
- —
| Function | Required | Pad(s) |
|---|---|---|
| I2C3.CLK | Yes | 4 |
| I2C3.DAT | Yes | 5 |
SPI1
SPI- Mode
- master, slave
- Max Clock
- —
- Address
- —
- Format
- —
| Function | Required | Pad(s) |
|---|---|---|
| SPI1.CS | No | 8 |
| SPI1.CLK | No | 9 |
| SPI1.MOSI | No | 10 |
| SPI1.MISO | No | 11 |
SPI3
SPI- Mode
- master, slave
- Max Clock
- —
- Address
- —
- Format
- —
| Function | Required | Pad(s) |
|---|---|---|
| SPI3.CLK | No | 2 |
| SPI3.CS | No | 3 |
| SPI3.MOSI | No | 6 |
| SPI3.MISO | No | 7 |
USART2
USART- Mode
- Max Clock
- —
- Address
- —
- Format
- —
| Function | Required | Pad(s) |
|---|---|---|
| USART2.RX | No | 6, 9 |
| USART2.TX | No | 8, 13 |
| USART2.RTS_DE | No | 10 |
| USART2.CK | No | 11 |
SAI1
SAI- Mode
- Max Clock
- —
- Address
- —
- Format
- —
| Function | Required | Pad(s) |
|---|---|---|
| SAI1.D2 | No | 3 |
| SAI1.CK2 | No | 4 |
| SAI1.MCLK_A | No | 4 |
| SAI1.SCK_A | No | 5 |
| SAI1.MCLK_B | No | 9 |
Development Product — This is an electronic development module intended for evaluation, prototyping, and integration into other designs by qualified engineers and developers. It is not a finished consumer product and has not been independently certified for FCC, CE, UL, or other regulatory compliance. The integrator of this module into a finished product is responsible for obtaining all necessary certifications. Not intended for use in life-support systems, safety-critical applications, or any application where failure could result in personal injury or property damage. See our Terms of Sale for full details.