HomeTile CatalogDrive.A.2
Bergsonne Labs

Drive.A.2

I2C/SPI-input dual 3W Class-D amplifier

The Drive.A.2 is a dual-channel audio output tile combining a DAC63202W 12-bit smart DAC with two TPA2028D1 Class-D audio power amplifiers. It provides two independent audio channels, each capable of delivering up to 3 W into 4 Ω or 880 mW into 8 Ω speakers.

The DAC63202W generates analog waveforms from digital data with 12-bit resolution and supports built-in waveform generation (sine, cosine, triangular, sawtooth) for processor-less tone generation. The DAC connects to a host processor via either I2C (up to 1 Mbps) or SPI (up to 50 MHz), auto-detected at power-on.

Each TPA2028D1 amplifier features I2C-programmable gain control (−28 dB to +30 dB in 1 dB steps), automatic gain control (AGC), and dynamic range compression (DRC) to prevent speaker overdrive and enhance perceived loudness. The amplifiers operate filter-free in Class-D mode for high efficiency and include thermal and short-circuit protection.

The tile operates from a 2.5 V to 5.5 V supply. All three ICs are controlled via a shared I2C bus, while the DAC can alternatively be driven over SPI for higher-bandwidth waveform updates.

Product Info

Status
Beta
In Stock
15
Pricing
QtyEach
1+$20.00
10+$18.00
50+$17.00

Technical Summary

Package
T44-10 (PDF)
Supplies
2.5–5.5V
Components
DAC63202W (PDF), TPA2028D1 (PDF)
Interfaces
I2CSPI

Resources & Links

Datasheet
Download PDF
JSON Tile Definition
v0.8 (Feb 16, 2026)
ECAD Libraries
Eagle|KiCad
Drivers
GitHub
Discussion
Discord

Application Notes

Automatic Bus Detection

The DAC in the Drive.A.2 tile automatically detects whether it is connected via I2C of SPI.

I2C Addresses

The Drive.A.2 can be configured for one of four I2C addresses by manipulating the connection of pad 3 (A0). Leaving the pad floating (or connecting to V+) uses the default address of 0x49. Connecting pad 3 to GND will change to address 0x48, while connecting to pad 3 to pad 4 (I2C.CLK) or pad 5 (I2C.DAT) will set the address to 0x4B or 0x4A, respectively.

Pad Assignments

12345678910T44-10(top view)
PadTypeFunctionNote
1GND
2DGPIOan internal 100k pull-up
SPIMISO
3DA0an internal 100k pull sets the default I2C address to 0x49.
SPIMOSI
4I2CCLK
SPICS
5I2CDAT
SPICLK
6OUT.0-
7OUT.0+
8OUT.1-
9OUT.1+
10V+2.5-5.5V

I2C

I2C
Mode
slave
Max Clock
1MHz
Addresses
0x49(default), 0x48, 0x4A, 0x4B
Format
FunctionRequiredPad(s)
I2C.CLKYes4
I2C.DATYes5

SPI

SPI
Mode
slave
Max Clock
50MHz
Address
Format
FunctionRequiredPad(s)
SPI.MISOYes2
SPI.MOSIYes3
SPI.CLKYes5
SPI.CSYes4

Development Product — This is an electronic development module intended for evaluation, prototyping, and integration into other designs by qualified engineers and developers. It is not a finished consumer product and has not been independently certified for FCC, CE, UL, or other regulatory compliance. The integrator of this module into a finished product is responsible for obtaining all necessary certifications. Not intended for use in life-support systems, safety-critical applications, or any application where failure could result in personal injury or property damage. See our Terms of Sale for full details.