BERGSONNE

Power

Battery life is about being asleep most of the time. core_power exposes the three low-power modes and the ways to wake from them — a timed RTC interval, a pin edge — plus backup registers that survive the deepest sleep. It sits on ll_pwr (there’s no HAL layer). Use the Core / HAL / LL toggle at the top of the sidebar to switch.

Overview

The modes trade wakeup latency and retained state against current draw. Picking one is mostly about what you need alive while asleep and how you’ll wake:

  • Sleep — CPU halted, peripherals and clocks running. Wakes on any interrupt, ~instantly. The everyday idle.
  • Stop — clocks halted, RAM retained. Wakes from EXTI or the RTC; the clock tree is rebuilt on wake.
  • Standby — almost everything off; RAM is lost and wakeup is a full reset. Lowest draw.

Sleep, stop & standby

The Core calls bundle entry, wakeup configuration, and (for stop) clock recovery into one call. core_sleep returns on the next interrupt; core_stop_for wakes itself after N seconds:

#include "core.h"

core_sleep();                 // idle until any interrupt

core_stop_for(3);             // Stop for 3 s (RTC), then resume with clocks restored

core_standby_for(60);         // Standby 60 s — wakes via full reset (never returns)
Standby resets on wake
core_standby_* never returns — the MCU resets. Detect it at the top of main() with core_woke_from_standby().

Wakeup & the RTC

Beyond a timed interval, you can wake on a pin edge, and the RTC gives you a wall clock with periodic wakeups and a calendar alarm:

// Wake from Stop on a falling edge on pad 8:
core_stop_until_on_change(8, EDGE_FALLING);

// RTC wall clock + alarm:
core_rtc_init();
core_rtc_set_time(12, 0, 0);
core_rtc_set_alarm(0xFF, 0xFF, 0);   // 0xFF = wildcard → fire every minute at :00
if (core_rtc_alarm_fired()) { ... }

Check core_woke_from_standby() first thing in main() to branch on a Standby return, then core_clear_standby_flag() to acknowledge it.

Backup registers

Backup registers are 32-bit slots that survive reset and Standby (and power loss, with VBAT). Use them for crash counters, boot flags, or carrying state across a Standby cycle:

core_backup_write(0, 0x12345678);
uint32_t saved = core_backup_read(0);   // persists across reset / Standby
Count varies by Core
CORE_BACKUP_COUNT is 32 on most Cores, 5 on the M0+ (Core.ST.L0).

Cross-architecture support

Sleep is verified across the family; Stop and Standby are further along on some Cores than others (Stop is hardware-verified on L4 and H5, compile-only elsewhere). RTC and backup registers are broadly available:

L0M0+L4M4W5M33H5M33WCH (RISC-V) · Nordic (nRF54) — in development

See the implementation status for the full matrix.

API reference

Power modes

Default-instance · Tier 2
void core_sleep(void);
Sleep until any interrupt (CPU stopped, peripherals running).
void core_stop_for(uint32_t seconds);
Enter Stop mode for a number of seconds, then wake and restore clocks. Uses RTC wakeup timer (LSI). Returns after wake with PLL + SysTick restored.
int core_woke_from_standby(void);
Returns 1 if the MCU woke from Standby.
Lower-level · Tier 1
void core_stop_until_on_change(uint8_t pad, uint32_t edge);
Enter Stop mode until a GPIO edge occurs on the given pad. Configures the pad as input, enables EXTI, enters Stop, and restores clocks on wake. Returns after the edge is detected.
void core_standby_for(void);
Enter Standby mode with RTC wakeup after the given seconds. Does not return — MCU resets on wake. Check core_woke_from_standby() at the top of main() to detect a Standby wake.
void core_standby_until_on_change(uint8_t pad, uint32_t edge);
Enter Standby mode until a GPIO edge on the given pad (via WKUP pin). Does not return — MCU resets on wake. Not all pads support WKUP; returns without entering Standby if the pad has no WKUP capability. On Core.ST.L4.2: pad 8 (PA0 = WKUP1) and pad 7 (PA2 = WKUP4).
void core_stop(void);
Enter Stop mode (caller manages wakeup source + clock recovery).
void core_standby(void);
Enter Standby (caller manages wakeup source). Does not return.
void core_clear_standby_flag(void);
Clear the Standby wake flag. Call after core_woke_from_standby() returns 1.
void core_watchdog_start_seconds(uint32_t seconds);
Start the independent watchdog with a timeout in seconds (convenience). For finer control use core_watchdog_start() from core_watchdog.h which accepts milliseconds.

Generated from core_power.htiles@2a1a847.

RTC

Default-instance · Tier 2
void core_rtc_init(void);
Initialize the RTC using LSI (~32kHz internal RC). Call once from `on start` before setting time, date, or alarms. For LSE, call ll_rtc_init(1) directly in hand-written C.
void core_rtc_set_time(uint8_t h, uint8_t m, uint8_t s);
Set the time (24h format).
void core_rtc_set_date(uint8_t y, uint8_t mo, uint8_t d, uint8_t wd);
Set the date.
void core_rtc_wakeup(uint32_t seconds);
Configure a periodic wakeup timer.
void core_rtc_wakeup_stop(void);
Disable the periodic wakeup timer.
void core_rtc_set_alarm(uint8_t hours, uint8_t minutes, uint8_t seconds);
Set Alarm A to trigger at a specific time. Pass 0xFF for hours, minutes, or seconds to ignore that field. The alarm fires when all non-masked fields match the RTC time.
void core_rtc_clear_alarm(void);
Clear the alarm (disable Alarm A).
int core_rtc_alarm_fired(void);
Check if the alarm has fired (poll mode). Clears the flag on read.
Lower-level · Tier 1
void core_rtc_get_time(uint8_t * h, uint8_t * m, uint8_t * s);
Read the current time.
void core_rtc_get_date(uint8_t * y, uint8_t * mo, uint8_t * d, uint8_t * wd);
Read the current date.

Generated from core_rtc.htiles@6bbf0d8.

Backup registers

Default-instance · Tier 2
uint32_t core_backup_read(uint8_t index);
Read a backup register.
void core_backup_write(uint8_t index, uint32_t value);
Write a backup register. Backup domain write access is enabled automatically.
Lower-level · Tier 1
void _core_backup_ensure_clk(void);
Ensure the RTC/backup register clock domain is accessible. On L0/L4 the backup registers live inside the RTC peripheral block, so RTCEN (and a clock source) must be active for reads AND writes. On WBA/H5 they're in TAMP, which only needs PWR+DBP.

Generated from core_backup.htiles@2a1a847.