Implementation status
The same core_* API and behavior DSL target every Core — this page is the honest map of how far each one is along, and where the platform is headed across architectures. One contract, many implementations.
Overview
A peripheral feature is “done” on a Core when the layers beneath the core_* API are implemented for that MCU and the result is checked on hardware. Because the contract is shared, this is the only thing that varies between Cores — so a single matrix captures the whole platform.
Today the shipping Cores are STMicroelectronics Arm Cortex-M parts. WCH (RISC-V) and Nordic (nRF54) Cores are in development; when they arrive they populate the same matrix without changing a line of your firmware.
Cores by architecture
Cores are named by vendor and series — Core.ST.L4, Core.CH.*, Core.N.*. The vendor segment is the architecture seam: everything above the core_* line is shared, everything below is re-implemented per family.
STMicroelectronics
· Arm Cortex-MShippingThe Cores shipping today, from an ultra-low-power M0+ up to a 250 MHz M33. The full feature matrix below is measured against these.
WCH
· RISC-VIn developmentRISC-V Cores bringing a lower-cost architecture to the same tile platform. The core_* API and behavior DSL are unchanged — only the layers beneath are re-implemented.
core_* contract, drivers via the PAL.Nordic
· Arm Cortex-M33In developmentnRF54 Cores adding modern wireless (BLE / 802.15.4) alongside the Arm M33 line. Same contract, same drivers via the PAL.
core_* contract, drivers via the PAL.Feature support matrix
Features by group, against the shipping Cores. Each entry carries the SDK layer it reaches (LL → HAL → TAL → Core); a layer implies everything beneath it.
| Feature | Layer | L0M0+ | L4M4 | W5M33 | H5M33 |
|---|---|---|---|---|---|
| System | |||||
| core initialization | Core | ● | ● | ● | ● |
| LED | Studio | ● | ● | ● | ● |
| delay (ms / µs) | Studio | ● | ● | ● | ● |
| SysTick | LL | ● | ● | ● | ● |
| fault handlers | ● | ● | ● | ● | |
| Clocks | |||||
| HSI (internal RC) | LL | ● | ● | ● | ● |
| HSE (external crystal) | LL | · | · | ● | · |
| MSI / MSIS (low-power) | LL | ◐ | ● | · | · |
| CSI (low-power internal) | LL | · | · | · | ● |
| PLL (high-speed) | LL | ● | ● | ● | ● |
| GPIO | |||||
| digital I/O (read / write) | Studio | ● | ● | ● | ● |
| EXTI (external interrupts) | Studio | ● | ● | ● | ● |
| alternate function config | LL | ● | ● | ● | ● |
| open-drain / pull config | Core | ● | ● | ● | ● |
| UART | |||||
| TX / RX (polling) | Core | ● | ● | ● | ● |
| interrupt-driven | Core | ● | ● | ● | ● |
| DMA | Core | ○ | ○ | ○ | ○ |
| hardware flow control | ○ | ○ | ○ | ○ | |
| LPUART (low-power) | Core | ● | ● | ● | ● |
| I2C | |||||
| standard mode (100 kHz) | Core | ● | ● | ● | ● |
| fast mode (400 kHz) | Core | ● | ● | ● | ● |
| fast-mode plus (1 MHz) | · | ● | · | ● | |
| interrupt-driven | Core | ○ | ○ | ○ | ○ |
| DMA | ○ | ○ | ○ | ○ | |
| 10-bit addressing | Core | ○ | ○ | ○ | ○ |
| SMBus mode | ○ | ○ | ○ | ○ | |
| SPI | |||||
| master TX / RX (polling) | Core | · | ● | ◐ | ● |
| interrupt-driven | Core | · | ○ | ○ | ○ |
| DMA | Core | · | ○ | ○ | ○ |
| slave mode | · | ○ | ○ | ○ | |
| OctoSPI / QSPI | · | · | · | ○ | |
| Timers | |||||
| basic timebase / tick | Studio | ● | ● | ● | ● |
| PWM output | Studio | ● | ● | ● | ● |
| input capture | Core | ● | ● | ○ | ● |
| one-shot pulse | ○ | ○ | ○ | ○ | |
| encoder mode | ○ | ○ | ○ | ○ | |
| LPTIM (low-power timer) | ○ | ○ | ○ | ○ | |
| IWDG (watchdog) | Studio | ● | ● | ● | ● |
| ADC | |||||
| single-shot raw read | Studio | ● | ● | ● | ● |
| millivolt read (VREFINT) | Studio | ● | ● | ● | ● |
| temperature sensor | Studio | ● | ● | ◐ | ● |
| resolution (8 / 10 / 12-bit) | Core | ● | ● | ◐ | ● |
| oversampling / burst | Core | ● | ● | ● | ● |
| DMA | Core | ● | ● | ● | ● |
| continuous / scan mode | Core | ● | ● | ● | ● |
| analog watchdog | ○ | ○ | ○ | ○ | |
| Project Generation (Coregen) | |||||
| GPIO pad auto-init | Core | ● | ● | ● | ● |
| I2C auto-init | Core | ● | ● | ● | ● |
| analog pad init | Core | ● | ● | ● | ● |
| SPI auto-init | Core | · | ● | ● | ● |
| UART auto-init | Core | ● | ● | ● | ● |
| timer / PWM auto-init | Core | ● | ● | ○ | ● |
| Power Management | |||||
| sleep mode | Core | ● | ● | ● | ● |
| STOP mode | Core | ● | ● | ● | ● |
| standby / shutdown | Core | ● | ● | ● | ● |
| RTC wakeup | Studio | ● | ● | ○ | ● |
| EXTI wakeup | Core | ● | ● | ○ | ● |
| wakeup pin (Standby) | Core | ○ | ● | ○ | ○ |
| RTC Alarm A | Studio | ● | ◐ | ● | ● |
| backup registers | Studio | ● | ◐ | ● | ● |
| Security | |||||
| hardware RNG | · | ● | ● | ○ | |
| AES (hardware) | · | ○ | ● | ○ | |
| PKA / ECC | · | · | ○ | · | |
| HASH (SHA-256) | · | · | · | ○ | |
| Connectivity | |||||
| USB CDC serial | Studio | · | ● | · | ● |
| USB HID | · | ○ | · | ● | |
| USB MSC | · | ○ | · | ○ | |
| ROM DFU bootloader | · | ● | · | ● | |
| BLE radio | · | · | ● | · | |
| BLE advertising | · | · | ● | · | |
| BLE GATT server | · | · | ● | · | |
| FDCAN | · | · | · | ○ | |
| Advanced | |||||
| I3C controller | · | · | · | ○ | |
| I3C target | · | · | · | ○ | |
| COMP (analog comparator) | ● | ● | ○ | · | |
| DAC | Studio | · | · | · | ● |
Legend
Status of each feature on each Core:
- ●Verified on hardware
- ●Compiles (not yet hardware-verified)
- ◐Partial
- ○Planned
- ·Not applicable to this MCU
The Layer column uses the SDK’s stack vocabulary — see SDK layers & API tiers. A higher layer implies the ones beneath it are present too.